Backplane Signal Assignments
There are two 96-pin connectors. I'll call them "left" and
"right" assuming you are viewing the card facing the connector edge
with the component side up. Each connector is broken down into three
32-pin sections, labelled "A", "B" and "C".
Note that when viewing the pins coming out of the backplane, "C" is on
top, "B" in the middle and "A" on the bottom (despite what
the wire-wrap tags say)
Left A
1 |
L0 |
Rcard |
Buffered output |
2 |
L1 |
Rcard |
Buffered output |
3 |
L2 |
Rcard |
Buffered output |
4 |
L3 |
Rcard |
Buffered output |
5 |
L4 |
Rcard |
Buffered output |
6 |
L5 |
Rcard |
Buffered output |
7 |
L6 |
Rcard |
Buffered output |
8 |
L7 |
Rcard |
Buffered output |
9 |
L8 |
Rcard |
Buffered output |
10 |
L9 |
Rcard |
Buffered output |
11 |
L10 |
Rcard |
Buffered output |
12 |
L11 |
Rcard |
Buffered output |
13 |
L12 |
Rcard |
Buffered output |
14 |
L13 |
Rcard |
Buffered output |
15 |
L14 |
Rcard |
Buffered output |
16 |
L15 |
Rcard |
Buffered output |
17 |
MAR0 |
Rcard |
Unbuffered 2-state output |
18 |
MAR1 |
Rcard |
Unbuffered 2-state output |
19 |
MAR2 |
Rcard |
Unbuffered 2-state output |
20 |
MAR3 |
Rcard |
Unbuffered 2-state output |
21 |
MAR4 |
Rcard |
Unbuffered 2-state output |
22 |
MAR5 |
Rcard |
Unbuffered 2-state output |
23 |
MAR6 |
Rcard |
Unbuffered 2-state output |
24 |
MAR7 |
Rcard |
Unbuffered 2-state output |
25 |
MAR8 |
Rcard |
Unbuffered 2-state output |
26 |
MAR9 |
Rcard |
Unbuffered 2-state output |
27 |
MAR10 |
Rcard |
Unbuffered 2-state output |
28 |
MAR11 |
Rcard |
Unbuffered 2-state output |
29 |
MAR12 |
Rcard |
Unbuffered 2-state output |
30 |
MAR13 |
Rcard |
Unbuffered 2-state output |
31 |
MAR14 |
Rcard |
Unbuffered 2-state output |
32 |
MAR15 |
Rcard |
Unbuffered 2-state output |
Left B
1 |
+5 |
|
|
2 |
Gnd |
|
|
3 |
IR0 |
Ccard |
Unbuffered |
4 |
IR1 |
Ccard |
Unbuffered |
5 |
IR2 |
Ccard |
Unbuffered |
6 |
IR3 |
Ccard |
Unbuffered |
7 |
IR4 |
Ccard |
Unbuffered |
8 |
IR5 |
Ccard |
Unbuffered |
9 |
IR6 |
Ccard |
Unbuffered |
10 |
IR7 |
Ccard |
Unbuffered |
11 |
PRIV |
Ccard |
raw mcode bits |
12 |
Gnd |
|
|
13 |
+5 |
|
|
14 |
L_FAULT |
Ccard |
High active, clocked |
15 |
ENCODER0 |
Ccard |
Priority encoder 0 |
16 |
ENCODER1 |
Ccard |
Priority encoder 1 |
17 |
ENCODER2 |
Ccard |
Priority encoder 2 |
18 |
ENCODER3 |
Ccard |
Priority encoder 3 |
19 |
_STOP_CKS |
FPcard |
|
20 |
MEMREF |
Ccard |
High active, not clocked |
21 |
LATCH_SZ |
Ccard |
Raw mcode bits |
22 |
Gnd |
|
|
23 |
MSWP |
Rcard |
Unbuffered |
24 |
MSWE |
Rcard |
Unbuffered |
25 |
MSWD |
Rcard |
Unbuffered |
26 |
MSWM |
Rcard |
Unbuffered |
27 |
MSWV |
Rcard |
Unbuffered |
28 |
MSWS |
Rcard |
Unbuffered |
29 |
MSWC |
Rcard |
Unbuffered |
30 |
MSWZ |
Rcard |
Unbuffered |
31 |
Gnd |
|
|
32 |
+5 |
|
|
Left C
1 |
A0 |
Mcard/Dcard |
Always buffered |
2 |
A1 |
Mcard/Dcard |
Always buffered |
3 |
A2 |
Mcard/Dcard |
Always buffered |
4 |
A3 |
Mcard/Dcard |
Always buffered |
5 |
A4 |
Mcard/Dcard |
Always buffered |
6 |
A5 |
Mcard/Dcard |
Always buffered |
7 |
A6 |
Mcard/Dcard |
Always buffered |
8 |
A7 |
Mcard/Dcard |
Always buffered |
9 |
A8 |
Mcard/Dcard |
Always buffered |
10 |
A9 |
Mcard/Dcard |
Always buffered |
11 |
A10 |
Mcard/Dcard |
Always buffered |
12 |
A11 |
Mcard/Dcard |
Always buffered |
13 |
A12 |
Mcard/Dcard |
Always buffered |
14 |
A13 |
Mcard/Dcard |
Always buffered |
15 |
A14 |
Mcard/Dcard |
Always buffered |
16 |
A15 |
Mcard/Dcard |
Always buffered |
17 |
A16 |
Mcard/Dcard |
Always buffered |
18 |
A17 |
Mcard/Dcard |
Always buffered |
19 |
A18 |
Mcard/Dcard |
Always buffered |
20 |
A19 |
Mcard/Dcard |
Always buffered |
21 |
A20 |
Mcard/Dcard |
Always buffered |
22 |
A21 |
Mcard/Dcard |
Always buffered |
23 |
CODE_PTB |
Ccard |
raw mcode bits |
24 |
USER_PTB |
Ccard |
raw mcode bits |
25 |
DBUS0 |
All cards |
Always buffered |
26 |
DBUS1 |
All cards |
Always buffered |
27 |
DBUS2 |
All cards |
Always buffered |
28 |
DBUS3 |
All cards |
Always buffered |
29 |
DBUS4 |
All cards |
Always buffered |
30 |
DBUS5 |
All cards |
Always buffered |
31 |
DBUS6 |
All cards |
Always buffered |
32 |
DBUS7 |
All cards |
Always buffered |
Right A
1 |
ALUOP0 |
Ccard |
Raw mcode bits |
2 |
ALUOP1 |
Ccard |
Raw mcode bits |
3 |
USE_CARRY |
Ccard |
Raw mcode bits |
4 |
ALUOP_SZ |
Ccard |
Raw mcode bits |
5 |
IMMVAL0 |
Ccard |
Raw mcode bits |
6 |
IMMVAL1 |
Ccard |
Raw mcode bits |
7 |
|
|
|
8 |
L_PTB |
Ccard |
NOR(decoded[LATCH],NCLKS) |
9 |
Gnd |
|
|
10 |
L_FPL |
Ccard |
Front Panel L latch signal |
11 |
Gnd |
Ccard |
|
12 |
_ER_MDR |
Ccard |
Decoded ER mcode bits |
13 |
_ER_IMM |
Ccard |
Decoded ER mcode bits |
14 |
_ER_FAULTCODE |
Ccard |
Decoded ER mcode bits |
15 |
Gnd |
|
|
16 |
_SET_FLAGS |
Ccard |
Decoded MISC mcode , unclocked |
17 |
Gnd |
|
|
18 |
INIT_INST |
Ccard |
Active high, clocked |
19 |
Gnd |
|
|
20 |
_EL_PTB |
Ccard |
Decoded EL mcode bits |
21 |
_EL_MAR |
Ccard |
Decoded EL mcode bits |
22 |
_EL_C |
Ccard |
Decoded EL mcode bits |
23 |
_EL_PC |
Ccard |
Decoded EL mcode bits |
24 |
_EL_DP |
Ccard |
Decoded EL mcode bits |
25 |
_EL_SP |
Ccard |
Decoded EL mcode bits |
26 |
_EL_A |
Ccard |
Decoded EL mcode bits |
27 |
_EL_B |
Ccard |
Decoded EL mcode bits |
28 |
_EL_MDR |
Ccard |
Decoded EL mcode bits |
29 |
_EL_SSP |
Ccard |
Decoded EL mcode bits |
30 |
_EL_TPC |
Ccard |
Decoded EL mcode bits |
31 |
_EL_MSW |
Ccard |
Decoded EL mcode bits |
32 |
+5 |
|
|
Right B
1 |
L_EI |
Ccard |
NOR(decoded[MISC],NCLKS) |
2 |
L_MODE |
Ccard |
AND(raw mcode,CLKS) |
3 |
L_PAGING |
Ccard |
AND(raw mcode,CLKS) |
4 |
L_MAR |
Ccard |
AND(raw mcode,CLKS) |
5 |
L_MDR_LO |
Ccard |
raw mcode (and'd w/ CLKS on Rcard) |
6 |
L_MDR_HI |
Ccard |
raw mcode (and'd w/ CLKS on Rcard) |
7 |
L_MSW |
Ccard |
NOR(decoded[LATCH],NCLKS) |
8 |
L_C |
Ccard |
NOR(decoded[LATCH],NCLKS) |
9 |
L_PC |
Ccard |
NOR(decoded[LATCH],NCLKS) |
10 |
L_DP |
Ccard |
NOR(decoded[LATCH],NCLKS) |
11 |
L_SP |
Ccard |
NOR(decoded[LATCH],NCLKS) |
12 |
L_MDR |
Ccard |
NOR(decoded[LATCH],NCLKS) |
13 |
L_SSP |
Ccard |
AND(LSP,OR(MSW[intrap],!MSW[mode])) |
14 |
L_A_LO |
Ccard |
NOR(decoded[LATCH],NCLKS) |
15 |
L_A_HI |
Ccard |
NOR(decoded[LATCH],NCLKS) & LATCH_SZ |
16 |
L_B_LO |
Ccard |
NOR(decoded[MISC],NCLKS) |
17 |
L_B_HI |
Ccard |
NOR(decoded[MISC],NCLKS) & LATCH_SZ |
18 |
FAULT_PENDING |
|
|
19 |
_L_PTE |
Ccard |
OR(decoded[MISC],NCLKS) |
20 |
Gnd |
|
|
21 |
L_IN_TRAP |
Ccard |
NOR(decoded[MISC],NCLKS) |
22 |
IN_TRAP |
Ccard |
FF on Ccard |
23 |
Gnd |
|
|
24 |
NEXT0 |
Card |
Microcode next address |
25 |
NEXT1 |
Card |
Microcode next address |
26 |
NEXT2 |
Card |
Microcode next address |
27 |
NEXT3 |
Card |
Microcode next address |
28 |
NEXT4 |
Card |
Microcode next address |
29 |
NEXT5 |
Card |
Microcode next address |
30 |
NEXT6 |
Card |
Microcode next address |
31 |
NEXT7 |
Card |
Microcode next address |
32 |
+5 |
|
|
Right C
1 |
_NP |
Mcard |
Unclocked, memref & page not present |
2 |
_NW |
Mcard |
Unclocked, memref & write & page not writeable |
3 |
_HALT |
Ccard |
Unclocked, decoded MISC |
4 |
COMMIT |
Ccard |
Clocked, decoded MISC | INIT_INST |
5 |
_TRAPO |
Ccard |
Unclocked, decoded MISC |
6 |
_DO_BRANCH |
Ccard |
Unclocked, decoded MISC |
7 |
_DO_RSHIFT |
Ccard |
Unclocked, decoded MISC |
8 |
_RESET |
External |
|
9 |
Gnd |
|
|
10 |
E_MDR_LO |
Ccard |
Inverted raw mcode |
11 |
E_MDR_HI |
Ccard |
inverted raw mcode |
12 |
_IRQ0 |
External |
Active low |
13 |
_IRQ1 |
External |
Active low |
14 |
_IRQ2 |
External |
Active low |
15 |
_IRQ3 |
External |
Active low |
16 |
_IRQ4 |
External |
Active low |
17 |
_IRQ5 |
External |
Active low |
18 |
FP_RAM |
Pcard |
Toggle, high if RAM, low if ROM |
19 |
_DMA_REQ |
External |
Active low |
20 |
_DMA_ACK |
Ccard |
Unclocked, decoded MISC |
21 |
FP_L0 |
Ccard |
Front panel select |
22 |
FP_L1 |
Ccard |
Front panel select |
23 |
FP_L2 |
Ccard |
Front panel select |
24 |
FP_L3 |
Ccard |
Front panel select |
25 |
_RW |
Ccard |
unclocked, 0 is read |
26 |
MEMORY |
Mcard |
0 for device, 1 for memory |
27 |
_E_PTE |
Ccard |
Unclocked, decoded MISC |
28 |
_FP_WRITE |
Pcard |
Debounced write pb, low active |
29 |
EXT_CLK |
Ccard |
External clock |
30 |
CLKM |
Ccard |
microcode clock |
31 |
CLKS |
Ccard |
system clock |
32 |
+5 |
|
|
|