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What's this?Here are links to the development diaries I've kept, along with some miscellaneous documentation Development Diaries
Stream of Consciousness Rantings
Miscellaneous DocumentationSerial port header pinoutsNot in the schematics are the pin assignments for the ribbon cable header for the two serial ports. Here they are:
Branch CodesThere will be two bits in the microcode to control conditional branches. These, combined with bits [1..3] of the opcode (ir[1..3]) will determine whether a branch is taken and on which condition. The branch instructions are scattered through the opcode space in order to match up the condition with bits 1..3. Note that there are two flavors of conditional branch: compare and branch (cmpb.<cond>) and branch on condition (br.<cond>). Within the microcode, the compare and branch instructions do a compare and branch on the condition codes produced by the operation. The two microcode bits are "branch" and "negate". If branch==0, we won't do an conditional branch. If it is 1, we'll select IR[1..3] to lookup the correct code and the output will be exclusive or'd with negate bit to provide the final branch code. In the microcode engine, if we don't take a branch, the sequencer reverts to location 0, the fetch microinstruction. Else, it continues with the address specified in the "next" field. For conditional branches, thatwould point to a sequence to add the displacement to pc to effect the branch. The "u" varieties are the unsigned comparisons. Note that I'm only supporting a subset of the branch codes for my atomic compare and branch, due to limited opcode space. I decided to fully support signed comparisons. Actually, not really fully -- I don't have greater than or greater than or equal. For these cases, I hope to be able to swap operand order and use the le and lt flavors. If for some reason my compiler can't easily do this, I can just do a compare and follow it with a branch on condition (which does have full condition support). Note also that I don't have any branch on overflow conditions I do have a trap on overflow, and you can also do a branch on bit of the flags register (after moving it to A). Here are the branch codes (note - redundancy in eq/ne needed because there are too many ops to fit into 1):
ALU CodesThese are getting a bit messy. We use ir[1..3] to select the code, but also need a few stragglers. To do a copy of the contents of the L bus to the Z bus, we will AND with imm(-1). For the compare operations, we need to explicitly select SUB because they fall all over the opcode map. The branch on bit opcodes can use AND, and the ADC, SBC and XOR stragglers must fall in the appropriate space in the opcode map. Further, we will have 8 and 16-bit operations, which will be controlled by the OPSIZE microcode bit. If OPSIZE==0, flags will be computed for an 8-bit result, and the ALU will only drive the low byte of the Z bus (and the high byte will be the extended sign of Z[8]. If OPSIZE==1, we'll do a 16-bit operation. Further, we need another bit to control carry-in. So, looks like we need 4 bits total:
The codes themselves are what is expected by the 74F381 4-bit alu parts.
Misc Notes [mostly historical]
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