mcode.h - Description of the fields within the microinstruction word.
	mcode.c - An initialized array representing the microcode image.
	mcdefs.h - #defines for microcode fields.
	prombits.h - The initialization declaration for the 512 56-bit microinstruction words.
	prom0.hex .. prom4.hex - Hex images of the slices of the microcode store to be fed into the PROM programmer.
	opcodes.h - Opcode strings.

//=====================================================
// BEGIN mcode.h
/* Define for micro instruction word.  Assume I'll be using 512x8 bipolar
 * PROMs.  This version is quite a bit more compact than previous ones,
 * but at the cost of having addition field decoding logic.  Initial plan
 * is to send these signals across the backplane and do decoding on the
 * appropriate card.
 *
 * Note that the encoding here is getting pretty ugly.  I'm trying hard to
 * keep the microcode store down to 5 PROMS - 16 bits for enable signals, 
 * 16 bits for latch signals and 8 bits for the next field. 
 */

typedef struct {
	unsigned next:8;	// Next micro-op to exec. 0x00 means
				// use output of priority encoder, 0xff
				// means use IR[0..7].  Also a significant
				// bit of !(IR[0..7]==0xff) to give the full
				// 9-bit microcode address.
	unsigned latch:4;	// Register latch signal. Value:
				// 0x0 : none
				// 0x1 : MSW (flag nibble only, from Z)
				// 0x2 : C
				// 0x3 : PC
				// 0x4 : DP
				// 0x5 : SP
				// 0x6 : A
				// 0x7 : B
				// 0x8 : MDR (from Z)
				// 0x9 : PTB
				// 0xa : [A low placeholder]
				// 0xb : [A high placeholder]
				// 0xc : [B low placeholder]
				// 0xd : [C low placeholder]
				// 0xe : [SSP placeholder]
				// 0xf : IR_REG (IR[5..7])
	unsigned lmar:1;	// Latch MAR
	unsigned lmdrlo:1;	// Latch MDR(lo) from dbus
	unsigned lmdrhi:1;	// Latch MDR(hi) from dbus
	unsigned emdrlo:1;	// Drive dbus with MDR(lo)
	unsigned emdrhi:1;	// Drive dbus with MDR(hi)
	unsigned priv:1;	// Priviliged instruction
	unsigned lmode:1;	// Latch (M)ode bit in MSW
	unsigned lpaging:1;	// Latch (P)aging enable bit in MSW
	unsigned misc:4;	// Controls signals which never occur at the
				// same time:
				// 0x0 : none
				// 0x1 : 
				// 0x2 : halt
				// 0x3 : 
				// 0x4 : trap on overflow
				// 0x5 : latch PTE
				// 0x6 : set flags (from alu op)
				// 0x7 : init_inst (clear MDR, PC->TPC, latch IR)
				// 0x8 : right shift alu output
				// 0x9 : DMA acknowledge
				// 0xa : latch MSW[ie] (Interrupt Enable)
				// 0xb : do branch
				// 0xc : latch MSW[in_trap]
				// 0xd : commit state
				// 0xe : 
				// 0xf : 
	unsigned e_l:4;		// Enable L bus
				// 0x0 : MAR
				// 0x1 : MSW
				// 0x2 : C
				// 0x3 : PC
				// 0x4 : DP
				// 0x5 : SP
				// 0x6 : A
				// 0x7 : B
				// 0x8 : MDR
				// 0x9 : PTB
				// 0xa : SSP
				// 0xb : TPC
				// 0xc : 
				// 0xd : 
				// 0xe :
				// 0xf : IR_BASE (4+IR[6..7])
	unsigned e_r:2;		// Enable R bus
				// 0x0 : MDR
				// 0x1 : Immediate
				// 0x2 : Fault code/encoder
				// 0x3 :
	unsigned immval:2;	// Immediate value
				// 0x0 : 0
				// 0x1 : 1
				// 0x2 : -2
				// 0x3 : -1
	unsigned aluop_size:1;	// 0x0 -> 16 bits, 0x1 -> 8 bits
	unsigned aluop:2;	// Which alu operation to perform
				// 0x0 : IR[1..3]
				// 0x1 : AND
				// 0x2 : SUB
				// 0x3 : ADD
	unsigned carry:1;	// 0x0 -> 0, 0x1 -> MSW[c]
	unsigned l_size:1;	// 0x0 -> latch byte, 0x1 -> latch word
	unsigned br_sense:1;	// 0x0 -> don't negate, 0x1 -> negate
				// Non-negated branch conditions are:
				// 	0x0 : eq
				// 	0x1 : eq
				// 	0x2 : lt
				// 	0x3 : le
				// 	0x4 : ltu
				// 	0x5 : leu
				// 	0x6 : eq
				// 	0x7 : ne
	unsigned user_ptb:1;	// User page table base override
	unsigned code_ptb:1;	// 0 to select data region of PTB, 1 for code
} mcode_rec_t;

extern mcode_rec_t mcode_store[512];
// END mcode.h

//=====================================================
// BEGIN mcode.c
//
#include "mcode.h"
mcode_rec_t mcode_store[512] = {
#include "prombits.h"
};

// END mcode.c

//=====================================================
// PREPROCESS prombits.h
// BEGIN mcdefs.h

// Register defines for LATCH() and EL() 
#define	R_MSW	1
#define	R_C	2
#define	R_PC	3
#define	R_DP	4
#define	R_SP	5
#define	R_A	6
#define	R_B	7
#define	R_MDR	8
#define	R_PTB	9
#define	R_SSP	10

// Register defines for LATCH()-only
#define	R_NONE	0
#define	R_IR_REG	15

// Register defines for EL()-only
#define	R_MAR	0
#define	R_TPC	11
#define R_FCODE	12
#define	R_IR_BASE	15

// Register defines for ER()
#define	ER_MDR	0
#define	ER_IMM	1
#define	ER_FAULT	2

// Defines for IMMVAL()
#define	IMM_0	0
#define	IMM_1	1
#define	IMM_NEG1	3
#define	IMM_NEG2	2

// Defines for MISC()
#define	M_NONE	0
#define M_SYSCALL 1
#define	M_HALT	2
#define M_BKPT 3
#define	M_TRAPO	4
#define	M_LPTE	5
#define	M_SET_FLAGS	6
#define	M_INIT_INST	7
#define	M_RSHIFT	8
#define	M_DMA_ACK	9
#define	M_LEI	10
#define	M_DO_BRANCH	11
#define M_CLR_TRAP	12
#define M_COMMIT 13

// Defines for ALUOP(op,size,carry)
#define	OP_IR13	0
#define	OP_AND	1
#define	OP_SUB	2
#define	OP_ADD	3
#define	WORD	0
#define	BYTE	1
#define	LWORD	1
#define	LBYTE	0
#define	NO_CARRY	0
#define	CARRY_IN	1

// Defines for CBR()
#define	B_NORMAL	0
#define	B_NEGATED	1

// END mcdefs.h

#define NEXT_POS	 0
#define LATCH_POS	 1
#define LMAR_POS	 2
#define LMDRLO_POS	 3
#define LMDRHI_POS	 4
#define EMDRLO_POS	 5
#define EMDRHI_POS	 6
#define PRIV_POS	 7
#define LMODE_POS	 8
#define LPAGING_POS	 9
#define MISC_POS	 10
#define E_L_POS		 11
#define E_R_POS		 12
#define IMMVAL_POS	 13
#define ALUOP_SIZE_POS	 14
#define ALUOP_POS	 15
#define CARRY_POS	 16
#define L_SIZE_POS	 17
#define BR_SENSE_POS	 18
#define USER_PTB_POS	 19
#define CODE_PTB_POS	 20

#define NEXT(VAL)	INIT(NEXT_POS,VAL)
#define LATCH(VAL)	INIT(LATCH_POS,VAL)
#define LMAR(VAL)	INIT(LMAR_POS,VAL)
#define LMDRLO(VAL)	INIT(LMDRLO_POS,VAL)
#define LMDRHI(VAL)	INIT(LMDRHI_POS,VAL)
#define EMDRLO(VAL)	INIT(EMDRLO_POS,VAL)
#define EMDRHI(VAL)	INIT(EMDRHI_POS,VAL)
#define PRIV(VAL)	INIT(PRIV_POS,VAL)
#define LMODE(VAL)	INIT(LMODE_POS,VAL)
#define LPAGING(VAL)	INIT(LPAGING_POS,VAL)
#define MISC(VAL)	INIT(MISC_POS,VAL)
#define E_L(VAL)	INIT(E_L_POS,VAL)
#define E_R(VAL)	INIT(E_R_POS,VAL)
#define IMMVAL(VAL)	INIT(IMMVAL_POS,VAL)
#define ALUOP_SIZE(VAL)	INIT(ALUOP_SIZE_POS,VAL)
#define ALUOP(VAL)	INIT(ALUOP_POS,VAL)
#define CARRY(VAL)	INIT(CARRY_POS,VAL)
#define L_SIZE(VAL)	INIT(L_SIZE_POS,VAL)
#define BR_SENSE(VAL)	INIT(BR_SENSE_POS,VAL)
#define USER_PTB(VAL)	INIT(USER_PTB_POS,VAL)
#define CODE_PTB(VAL)	INIT(CODE_PTB_POS,VAL)

#define CBR(SENSE,TGT)	MISC(M_DO_BRANCH),BR_SENSE(SENSE),NEXT(TGT)
#define L(REG,SIZE)	LATCH(REG),L_SIZE(SIZE)
#define	USE_IR	0xff
#define READLO LMDRLO(1)
#define READHI LMDRHI(1)
#define READEXT LMDRLO(1),LMDRHI(1)
#define WRITELO EMDRLO(1)
#define WRITEHI EMDRHI(1)
#define	INC_TO_Z(REG) E_L(REG),E_R(ER_IMM),IMMVAL(IMM_1),ALU(OP_ADD,WORD,NO_CARRY)
#define INC2_TO_Z(REG) E_L(REG),E_R(ER_IMM),IMMVAL(IMM_NEG2),ALU(OP_SUB,WORD,NO_CARRY)
#define	DEC_TO_Z(REG) E_L(REG),E_R(ER_IMM),IMMVAL(IMM_NEG1),ALU(OP_ADD,WORD,NO_CARRY)
#define	ZERO_TO_Z E_L(R_MDR),E_R(ER_IMM),IMMVAL(IMM_0),ALU(OP_AND,WORD,NO_CARRY)
#define NEG1_TO_Z E_L(R_MDR),E_R(ER_IMM),IMMVAL(IMM_NEG1),ALU(OP_ADD,WORD,NO_CARRY)
#define TO_Z(REG) E_L(REG),E_R(ER_IMM),IMMVAL(IMM_NEG1),ALU(OP_AND,WORD,NO_CARRY)
#define TO_Z8(REG) E_L(REG),E_R(ER_IMM),IMMVAL(IMM_NEG1),ALU(OP_AND,BYTE,NO_CARRY)
#define	LDHI READHI,INC_TO_Z(R_MAR),LMAR(1)
#define LDLO READLO,TO_Z(R_PC),LMAR(1) 
#define STHI WRITEHI,INC_TO_Z(R_MAR),LMAR(1)
#define STLO WRITELO,TO_Z(R_PC),LMAR(1)
#define LDIMMHI CODE_PTB(1),READHI,L(R_PC,LWORD),INC_TO_Z(R_PC),LMAR(1)
#define LDIMMLO CODE_PTB(1),READLO,L(R_PC,LWORD),INC_TO_Z(R_PC),LMAR(1)
#define LDIMMEXT CODE_PTB(1),READEXT,L(R_PC,LWORD),INC_TO_Z(R_PC),LMAR(1)
#define GEN_ADDR(BASE) E_L(BASE),E_R(ER_MDR),ALU(OP_ADD,WORD,NO_CARRY)
#define COMPARE_0(REG) E_L(REG),E_R(ER_IMM),IMMVAL(IMM_0),ALU(OP_SUB,WORD,NO_CARRY)
#define ALU(OP,SZ,CRY) ALUOP(OP),ALUOP_SIZE(SZ),CARRY(CRY)
#define FETCH_OP CODE_PTB(1),READLO,MISC(M_INIT_INST),INC_TO_Z(R_MAR),L(R_PC,LWORD),LMAR(1),NEXT(UNUSABLE)